1. Field of the Invention
The present invention relates to activation control of word lines in a semiconductor memory device having a memory array, in which dynamic memory cells are arranged in a matrix.
2. Description of the Related Art
Typically used semiconductor memory devices are DRAMs and SRAMs. As is well known in the art, the DRAM is more moderately priced and has the larger capacity than the SRAM but requires refresh operations. The SRAM does not conveniently require refresh operations, but is more expensive and has the smaller capacity than the DRAM.
A known virtual SRAM (VSRAM: Virtually Static RAM) has been developed as the semiconductor memory device having the advantages of both the DRAM and the SRAM. The virtual SRAM (also called pseudo SRAM (PSRAM: Pseudo Static RAM)) has a memory cell array of dynamic memory cells like the DRAM and a built-in refresh timer to internally execute refresh operations. An external device (for example, a CPU) connecting with the virtual SRAM can thus gain access to the virtual SRAM to write and read data without specifically noticing refresh operations. This characteristic of the virtual SRAM is called ‘permeability of refresh operations’.
The prior art virtual SRAM executes the refresh operation according to its working state. For example, in a working state where an external access is executed (hereafter referred to as ‘operation mode’), the virtual SRAM specifies a refresh execution timing to execute a refresh operation, in response to an external access timing signal representing the timing of an external access after generation of a refresh timing signal that is output at preset intervals by the refresh timer. In another working state where no external access is executed (hereafter referred to as ‘standby mode’), the virtual SRAM specifies the refresh execution timing to execute the refresh operation, in response to generation of the refresh timing signal.
The cycle time (refresh cycle time) of the generation cycle (refresh cycle) of the refresh timing signal may be set as discussed below. The prior art virtual SRAM is designed to refresh memory cells in units of rows. When the refresh cycle time is Trc and the number of rows included in the memory cell array is m (where m is an integer of not less than 1), a total refresh time Tsum required for refreshing all the memory cells is equal to the m-fold of the refresh cycle time Trc (m·Trc). The refresh operation of one memory cell is executed at every refresh time Tsum. The value of the refresh cycle time Trc is thus set to ensure storage of data, while each memory cell is refreshed at every refresh time Tsum.
The refresh operation in the virtual SRAM is, for example, disclosed in Japanese Patent Laid-Open Gazette No. 2002-74945.
The prior art virtual SRAM generates the external access timing signal, in response to a variation of an externally input address. No variation of the external address leads to non-generation of the external access timing signal, even in the case of generation of the refresh timing signal. In this case, the refresh execution timing is not specified and the refresh operation is delayed.
The delayed refresh operation extends the refresh time Tsum and thereby lengthens the interval of the refresh operation of each memory cell. This undesirably increases the possibility of losing data. As the countermeasure against this problem, the prior art virtual SRAM generally imposes the restriction of ‘prohibiting a continuous access to an identical address for or over a preset time period’ (referred to as ‘long rate restriction’ or ‘long cycle restriction’.
The SRAM does not have this long rate restriction. The prior art virtual SRAM is thus required to improve the permeability of the refresh operation and to eliminate the long rate restriction.